In current high-speed memory or computing systems, the data bus width can be 64-bits wide, as in SDRAM (synchronous DRAM) or DDR SDRAM (double data rate synchronous DRAM) memory systems. The wide bus provides a greater amount of communication bandwidth for the system for a given bandwidth per path on the bus. The bandwidth of an individual path is usually dictated by parasitic capacitances on the bus, bus length, and physics. Therefore, there are fixed maximum transmission limits on individual paths. A clock or reference signal is used to provide a time reference for when the data is valid and can be reliably latched into a receiving device. High data rates on the bus only provide a very narrow margin of time in which the data is valid for a given bit time. This time is often only hundreds of picoseconds long. The clock or reference signal must therefore be very stable and properly centered in a data valid window of a device receiving or transmitting data to ensure proper data transfers along the bus.
In bus systems, receiving devices along the bus will typically receive the same information at different points in time, due to the propagation delay of the bus. Therefore, a stable clock sent along a bus path will be received at the receiving devices at different points in time. In high-speed systems, the clock is usually transmitted in the same direction and over a similar path as the data, so the relative position of clock and data is maintained at each receiving device. This is a fundamental scheme used by most source synchronous bus systems, or bus systems utilizing clock forwarding. Accordingly, the larger the clock timing differences from device to device along the bus, the greater the complexity in ensuring proper data transfer on the bus.
To assist data transfer, some bussed systems, such as DDR SDRAM memory systems, use a bursty data strobe as a reference clock. The strobe will only toggle when data is valid on the bus. This approach provides a good indication as to when data is valid; however, the fact that the strobe does not run continuously can make system design more difficult since phase locked loops cannot be used for clock buffering.
In wide bussed systems, e.g. 64 bits, an individual device, e.g. an individual memory device, on the bus may only have an 8-bit data width (ignoring parity bits). Therefore, a transmitting/receiving location on the bus may be comprised of eight such devices in parallel (8×8=64 bits). Additionally, the bus will have depth, and there can be several transmitting/receiving locations on the bus. Since the clock must be distributed to all eight devices cross the bus at the same time, there is an eight device loading of the clock path on the bus. On the other hand, each of the data signal paths would have only one connection to the bus at a transmitting/receiving device location. Therefore, a single clock sees eight times more line loading than does the data. Because of this, it is difficult for the clock line to have as high of bandwidth as the data lines due to such excessive loading, and due to the stubbed bus connections to all of the devices on the bus which cause reflections. Further, the extra loading capacitance would not allow the clock signal to propagate along the bus at the same velocity as the data signal.
To maintain high bandwidth on the clock signal, a plurality of clock signals can be replicated by the driving source (such as the controller or clock driver) and provided on respective clock lines of the bus. However, the disadvantage of this approach is that a large number of total clock signal lines and interconnect lines are required on the bus and the bus connectors.
When a clock is forwarded with the data in a bi-directional bus, there are usually two clocks required—one clock for each direction. Therefore, each data transmitting/receiving device on the bus may have two time domains—one time domain for receiving data, and another time domain for transmitting data. The receiving device will ultimately have its own master time domain that governs the synchronicity of the logic circuits within the device. Methods must therefore be provided to transfer data from the received time domain or the transmit time domain to the master time domain for the device. This data handoff can be difficult if the data arrival or transmit times vary significantly relative to the clock period of the device. A method must be used to guarantee a reliable handoff (so that internal latch setup or hold times are not violated) within the device. In some systems, an input or output FIFO is used to allow the data from one time domain to be buffered and become stable while the other time domain pulls the data from the FIFO. However, the FIFO's add some delay or latency to the system since typically two or more FIFO stages must be filled prior to emptying the FIFO on the other side. If the clocks from the two time domains can be adequately lined up to a convenient phase relationship, the latch setup and hold times can be guaranteed without using a FIFO. The problem arises when an inconvenient phase relationship occurs due to differences in signal flight times of the data and clock, or changes in flight time of one or the other.
Accordingly, a simplified data transmission bus system which mitigates at least some of these limitations and complexities of the bus systems described above and which will allow high speed operation is desired.